Cadence Design Systems Sigrity v19.00.000-2019 x64  (藍光)幫助PCB設計團隊縮短設計週期的同時實現設計成本和性能的最優化
美國Cadence公司近日宣佈發佈CadenceSigrity2019版本，該版本包含最新的3D解決方案，幫助PCB設計團隊縮短設計週期的同時實現設計成本和性能的最優化。獨有的3D設計及分析環境，完美集成了Sigrity工具與CadenceAllegro技術，較之於當前市場上依賴於第三方建模工具的產品，Sigrity2019版本可提供效率更高、出錯率更低的解決方案，大幅度縮短設計週期的同時、降低設計失誤風險。此外，全新的3DWorkbench解決方案彌補了機械和電氣領域之間的隔閡，產品開發團隊自此能夠實現跨多板信號的快速精準分析。

由於大量高速信號會穿越PCB邊界，因此有效的信號完整性分析必須包括信號源、目標芯片、中間互連、以及包含連接器、電纜、插座等其它機械結構在內的返回路徑分析。傳統的分析技術為每個互連器件應用單獨的模型後，再將這些模型在電路仿真工具中級聯在一起，然而，由於3D分開建模的特性，從PCB到連接器的轉換過程極易出錯。此外，由於3D分開建模很可能產生信號完整性問題，在高速設計中，設計人員也希望從連接器到PCB、或是插座到PCB的轉換過程可以得到優化。

x64|Languages:English| 

Description:
Sigrity2019softwareforsimulationandsignalintegrityinhigh-frequencycircuits.Withtheadvancementofdigitalprocessingtechnology,theneedforfasterprocessinghasgrownincreasingly,Prdzashgrhayythatnecessarilyneedstoworkfastercircuitswithhigherprocessingspeedsandhigherfrequenciesarelocated.ByincreasingthespeedsignalsforaccuratespeedupthesignalsonroutesthataremountedonboardsPCBorboardslaminatedissuesandnewproblemsarisesinthecaseofField,grippedengineerswillbeeventssuchasinterference,distortionandnoiseandsignalintegrityathighfrequenciescausetobesubjecttothreats.

Tominimizethesethreats,compensatethemandincreasethequalityofhigh-speedcircuits,needsanalysisandcorrectiveactionsthatthesoftwareAllegroSigrityitisconvenientforus.Thesoftwarecombinestechnologywithdesign,editingandroutingICandPCBcoordinateCadence®Allegro®enablesadvancedanalysisofbothpre-layoutandpost-layoutprovidesforusers.

Thesoftwareisdesignedtoexaminevariousscenariosintheinitialphasesallowsaccuratedesignandredesignminimized.ThissoftwaresupportsreadingandwritingdirectlyonthePCBandICdesignofAllego'sdatabase.AccuratesimulatorbasedonSPICEaswellasbuilt-solverfor2dand3dextractstheuser.Thesoftwarealsomodelingthetransistor-levelinputandoutputfunctionsincludepower-awareIBIS5.0support.

FeaturesandApplicationsAllegroSigrity:
-PerformawiderangeofSIanalysisorSignalintegrity(signalintegrity)
-Earlydetectionofdesignerrorstoincreasesuccessintheearlyphases
-Restrictionscanbesetquicklyandaccuratelyapplythebasicprocesses
-Improveproductperformancethroughexplorationandspacesolutions
-Evaluationofalternativetopologiesininfancy
-ProductionofSparametersofthetopologyandsignalanalysisintheformofparameterS
-Tablesestimateinterferencedesignedtoincreaseproductivity
-WasapprovedafterPCBdesignandICdesigndirectlyonboards
-Multipleevaluationandconfirmationsignalsfordifferentpathsonsiliconboards

Sigrity2019ReleaseAcceleratesPCBDesignCyclesbyIntegrating3DDesignand3DAnalysis:

InterconnectModelingTechnology:
-UpgradedinterconnectmodelingtechnologyaddresseslatesttrendsonPCBandICpackagedesign.Withsignalspeedsclimbingto32Gbpsandfaster,theneedtostrategicallymodelPCBsandconnectorsasonestructureisnowrequired.ThenewCadence®Sigrity™3DWorkbench,includedwiththeSigrityPowerSI3DEMExtractionOption(3DEM),allowsuserstoimportmechanicalstructures,suchascablesandconnectors,andmergethemwiththePCB.Thiswaycritical3Dstructuresthatcrossfromtheboardtotheconnectorcanbemodeledandoptimizedasonestructure.UpdatestothePCBcanbeautomaticallyback-annotatedtothePCBlayouttool.

The3DWorkbenchoffers:
-SIandPIapplications
-Afamiliar3Dlookandfeel
-Abilitytoimportmechanicalstructures
-Abilitytoimportelectricaldatabasesandmergewithmechanicalstructures
-3Dsolidmodeling(parametricandfullfeatured)
-Simulationof:
-Twistedpairwiring(cables)
-Backplaneplusconnectors
-Connectormodeling(HDMI,SATA,etc.)
-SMAconnectoronaPCB

Rigid-FlexSupport:
Industry-firstfullRigid-FlexPCBextractionfromasinglelayoutdatabaseprovidesaccurateinterconnectmodelingofbothrigidandmeshed-groundflexcablezones.Thezoneinformationisautomaticallyimportedfromversion17.2ofCadenceAllegro®technology.

FasterICPackageModeling:
-ICpackagemodelingofdesignswiththousandsofbumps/ballsisnow3Xfasterandmemoryconsumptionhasbeenreducedby75percent.

PowerIntegrityUpdates:
-Upgradedpowerintegrity(PI)technologyaddressesnewcheckingrequirementsandnewusabilityrequirementsforPCBfront-to-backdesignflows.Manyenhancementshavebeenadded,includinghierarchicalviews,quicksearch,andfiltering,comparisontreereport,andtooltips.

AllegroPowerTree™technology:
-TheDCanalysistechnologyhasbeenupgradedtosupportintegrationwithAllegrotechnology,HTMLblock-diagramenhancements,andautomatedadd-nodes-on-padsenhancements.

SigrityPowerDC™technology:
-TheACanalysistechnologyhasaddedsomeadditionalchecksthatnowlookattheweightedACcurrentandchecksforequalvoltage.Newbatch-mode“projects”allowthesetwonewworkflowsaswellasotherstobesetupasasetofbatchchecks.

SigrityOptimizePI™technology:
-Upgradedsignalintegrity(SI)technologyacceleratesthetimeittakestoverifymemoryinterfaces,seriallinks,andtheplethoraofothersignalsonaPCBthatcancauseadesigntofailinthelab.Thetechnologynowfeaturesworkflowsandvisionsthatcanbeusedtoquicklyperformelectricalrulechecksthatfindimpedancevariationsandexcessivecoupling.Thesechecksrequirenomodelsandcanberunbybothexpertandnon-expertsinsignalintegrity.

SystemRequirements:
OS:Microsoft®Windows®7allversions(64-bit),Windows10(64-bit),Windows2012Server(Allservicepacks),Windows2016Server(Allservicepacks).
Note:Note:Clarity3DSolverandCelsiuswithHyper-VarenotsupportedonWindows7.
CPU:Intel®Core™i74.30GHzorAMDRyzen™74.30GHzwithatleast4cores
RAM:8GBRAM/64GBRAMorhigher
Space:50GBfreediskspace/500GBfreediskspaceSSDisrecommendedforprimaryoperatingsystem(OS)andsimulationworkingdirectory
Internet:Microsoft®InternetExplorer®9.0orlater
Display:1,024x768displayresolutionwithtruecolor(16bitcolor)/Largemonitor(ortwo)withFullHDresolutionorhigher
GPU:Dedicatedgraphicscardwith1GBvideomemoryorhigher

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