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| 商品编号: |
DVD12239 |
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| 商品名稱： |
Mentor Graphics ModelSim SE-64 10.7-HDL仿真環境軟件 |
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| 碟片數量： |
1片 |
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| 銷售價格： |
100 |
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| 瀏覽次數： |
10015 |
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【轉載TXT文檔】 |
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| Mentor Graphics ModelSim SE-64 10.7-HDL仿真環境軟件 |
Mentor Graphics ModelSim SE-64 是Mentor Graphics的一種多語言HDL仿真環境，用於仿真硬件描述語言，如VHDL，Verilog和SystemC，并包含一個內置的C調試器。ModelSim可以單獨使用，也可以與Intel Quartus Prime，Xilinx ISE或Xilinx Vivado一起使用。
它採用直接優化的編譯技術、Tcl/Tk技術、和單一內核仿真技術，編譯仿真速度快，編譯的代碼與平台無關，便於保護IP核，個性化的圖形界面和用戶接口，為用戶加快調錯提供強有力的手段，是FPGA/ASIC設計的首選仿真軟件。
Mentor Graphics ModelSim SE-64 10.7 |
Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.
About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused.
In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.
The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
Product: Mentor Graphics ModelSim
Version: SE 10.7
Supported Architectures: x64
Website Home Page : http://www.mentor.com
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer
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