作為全球電子設計創新的領導者，Cadence設計系統公司推出了15.13版物理驗證系統（PVS），它是首款簽收解決方案，支持設計和後端物理驗證，約束驗證和可靠性檢查。
該系統集成了業界標準的Cadence Virtuoso定制/模擬，Cadence Innovus數字設計和混合信號流。這為您提供了與所有Cadence工具集成的端到端設計和簽核物理驗證解決方案。
通過PVS，您可以放心地完成高級節點設計簽收檢查（DRC和LVS）。代工廠提供PVS規則套件，PVS提供高效，全面的調試工具，以減少調試時間並提高生產力。
該解決方案支持先進的工藝節點技術（如雙重圖案化，三重圖案化，四重圖案化，3D-IC，FinFET規則，先進的器件提取等），並將物理驗證技術擴展到設計可靠性檢查和約束驗證。 PVS還提供分佈式處理能力，在不需要專門硬件的情況下大大加快了吞吐量。
Cadence Design Systems, Inc., the leader in global electronic design innovation, has presented 15.13 version of Physical Verification System (PVS) is the premier signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
The system integrates with industry-standard Cadence Virtuoso custom/analog, Cadence Innovus digital design, and mixed-signal flows. This provides you with an end-to-end design and signoff physical verification solution integrated with all Cadence tools.
With PVS, you can complete advanced-node design signoff checks (DRC and LVS) with peace of mind. Foundries provide the PVS rule decks, and PVS provides efficient, comprehensive debug tools to reduce debug time and increase productivity.
This solution supports advanced process node technologies (such as double patterning, triple patterning, quadruple patterning, 3D-IC, FinFET rules, advanced device extraction, and more), and it extends physical verification technology into design reliability checking and constraint validation.
PVS also offers a distributed processing capability that greatly accelerates throughput without requiring specialized hardware.
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